Storage tube



Sept. 10, 1968 J. R. CRICCHI ET AL 3,401,294

STORAGE TUBE Filed Feb. 8, 1965 2 Sheets-Sheet 1 I l was @9 FIG. 3. 7278 1 6g 73 68 i 7 7 72 7874 A A 1 1. K; \\l\ 78 8| '80 8 9 as s2 66 7a69 7o 78 8| 76 J INVENTORS 999 16 9 James R, cricchi and e 0 ea e WslferG. Reininger so E I )1 8 2 M 67A 69A ATTORNEY 3,401,294 STORAGE TUBEJames R. Cricchi and Walter G. Reininger, Catonsville, -Md., assignorsto Westinghouse Electric Corporation,

East Pittsburgh, Pa., a corporation of Pennsylvania Filed Feb. 8, 1965,Ser. No. 431,027 17 Claims. (Cl. 313-68) This invention relatesgenerally to electron discharge devices and more particularly toimproved storage targets for use in electronic storage tubes.

In conventional electronic storage tubes, information is Written onto atarget element typically made of a relatively thin layer of a dielectricmaterial. The information is'written onto the surface of the dielectrictarget by means of an electron beam (writing beam) and is stored in theform of a pattern of charges established on the surface of that target.The establishment of these charges may be accomplished either bycreating a secondary emission effect or by inducing a current within thedielectric by electron bombardment. After the elapse of a given periodof time, the information may be retrieved by directing a beam ofelectrons (reading beam) to scan the target and derive an output signalin accordance with the pattern of charges.

As may be seen from the above discussion, the storage capability isachieved by placing a pattern of charges on the surface of thedielectric material. The pattern of charges will remain on the surfaceof the dielectric material until they are deliberately erased or untilthe charges are discharged through the dielectric material. Inherently,the capacity and resistance of the dielectric material are finite, andas a result an electrical path is established through the dielectricmaterial to the electrodes and support structure associated with theaforementioned dielectric material to dissipate the pattern of chargesplaced on the surface of the dielectric material. In a typical storagetube, the dielectric material is deposited on a planar electrode of aconductive material in order to establish the target element at aspecified voltage or to provide an electrode through which the outputsignal may be derived. In any event it may be understood that such anelectrode would provide an intimate electrical path through which thesurface charge on the dielectric material may be dissipated, and as aresult the period for which the information may be stored is therebylimited.

Further in typical electrostatic storage tubes, it is often necessary tomaintain a potential upon the target element in order that the targetelement will maintain its storage function; therefore considerablequantities of electrical power are often required for the operation ofthese devices.

Specifically, there is known in the prior art an electronic storagedevice in which the electric field established by a pattern or chargesestablished on a thin layer of a dielectric material is utilized toeffect the impedance across a reverse biased, rectifying junction. Thereverse biased rectifying junction, as suggested by the prior art, isestablished by a conductive lead which is inserted through or in closeproximately with the storage layer of dielectric material to a membercomposed of a semiconductor material to form therebetwee n a pointcontact junction. The principle of this device lies in the effect of theelectric field created by the storage charges upon the impedanceestablished by the junction of the point contact. In a typical pointcontact diode, a voltage source may be applied across the junction sothat the junction will exhibit a high resistance by biasing the voltagesource to oppose the flow of the charge carriers within thesemiconductor material across the junction. In the aforementionedstorage device of the prior art, the electric field established nitedStates fltent 3,401,294 Patented Sept. 10, 1968 by the charges stored onthe dielectric material will effect the lmpedance established by thepoint contact junction. Therefore, in operation, a specified charge maybe placed on the layer of dielectric material which may be detected orread out by placing a reverse bias across the point contact junction.Further, the target element suggested by the prior art may be composedof a plurality of these point contact junctions disposed in a regulararray; thus, a pattern of information may be stored on the targetelement and may be successively read out by applying successively areverse bias to each of the point contact unctions.

However, the storage device as described above does have significantlimitations in several aspects of its operatron. First, the highresistance junctions are formed by conductive leads which are intimatelyassociated with the storage dieletcric layer and which tend to dissipatethe charge from the storage layer. Thus, it may be seen that the periodsof time for which a signal pattern may be stored are limited. Furtherdue to the proximity of the storage layer and the lead, the Writingelectron beam may interfere with the readout operation; therefore, it isnecessary to operate the reverse biasing voltage at a level whose orderof magnitude is substantially above that of the reading beam ofelectrons. Thus, it may be understood that the dynamic range and thedegree of amplification provided by such a target may be so limited soas to allow only a digital mode of operation of this target. Morespecifically, the dynamic range of such a target is limited by thereverse leakage currents of the point contact junctions of this target.In addition, no isolation has been provided by the storage device of theprior art to electrically separate each of the point contact junctions;therefore, such a target element would be limited to a single mode ofread out in which the rectifying junctions are successively read out oneat a time. Finally, it would be quite diflicult and time consuming toform a sufficient number of the point contact junctions to provide astorage target having a reasonably high resolution.

Accordingly, it is an object of this invention to provide an electronicstorage tube having an improved storage target.

A further object of this invention is to provide an improved storagetarget in which the electrical contacts thereto are substantiallyisolated from the storage dielectric layer thereof.

A still further object of this invention is to provide an improvedstorage target in which a sufficient number of reverse biased,rectifying junctions may be arrayed to provide a target element capableof very high resolution.

A still further object of this invention is to provide an improvedstorage target which may be easily manufactured without the necessity ofperforming a great number of repetitive steps to form each of thereverse biased rectifying junctions.

Still another object of this invention is to provide an improved storagetarget in which the high number of reitifying junctions are effectivelyisolated from each ot er.

Another object of this invention is to provide an improved storagetarget in which distinct rectifying junctions may be simultaneously readout to thereby allow various portions of the target element to beoperated in different modes of operation.

Still another object of this invention is to provide an improvedelectronic storage target in which the read out of the rectifyingjunctions may be performed to sense the varying levels of charge storedon the dielectric layer to thereby achieve an analog mode of operation.

A still further object of this invention is to provide a storage targethaving great sensitivity and capable of being operated over a widedynamic range.

Stated briefly, the electronic storage tube in accordance with thepresent invention comprises a cathode element for directing a writingbeam of electrons onto an improved target element. The storage target ofthis invention is made of a first layer of a dielectric material, amemory unit formed by planar diffused junctions disposed beneath thesurface of said dielectric storage layer, and a plurality of electricalcontacts disposed remotely from said dielectric storage layer to providemeans for applying a reverse bias voltage across the planar diffusedjunctions. In one particular embodiment of this invention, the planardiffused junction is formed by diffusing N carriers in one region of asemiconductor crystal and P carrier into an adjacent region of thesemiconductor crystal. It is a further aspect of this invention that theplanar diffused junction be isolated from the other such junctions ofthe target element. This may be accomplished by inserting additional PNjunctions between each of the memory units formed by the planar diffusedjunctions.

Further objects and advantages of the invention will become apparent asthe following description proceeds and features of novelty whichcharacterize the invention will be pointed out in particularity in theclaims annexed to and forming a part of this specification.

For a better understanding of the invention reference may be had to theaccompanying drawings, in which:

FIG. 1 is a sectioned view of an electronic storage tube utilizing thepresent invention;

FIG. 2 is a perspective view of the storage target incorporated in thestorage tube shown in FIG. 1;

FIG. 3 is a cross-sectional view of an embodiment of FIG. 2 taken alongline IIIIII of FIG. 2;

FIG. 4 is a diagrammatic view of the electrical circuit of the storagetarget as shown in FIGS. 2 and 3;

FIG. 5 is an enlarged plan view of the reverse side of the storagetarget shown in FIG. 2;

FIG. 6 is a cross-sectional view of an embodiment of FIG. 5 taken alongline VI-VI of FIG. 5; and

FIG. 7 is a schematic view of the interconnections made to the storagetarget of this invention.

Referring now to the drawings and in particular to FIG. 1, a memory tube10 is depicted as comprising an evacuated envelope 12 having a neckportion 14 axially aligned of and interconnected to a flared portion 16.The neck portion 14 and the flared portion 16 which are made of glass orother suitable material, are respectively connected to a base 18 throughwhich terminals 20 are inserted and to an annular flange 22 made of asuitable material such as Kovar (a Westinghouse trademark for I an alloycomprised substantially of iron, nickel, and cobalt). A mountingcylinder 24 has a radially extending flange 25 which is secured to theannular flange 22 by a suitable method such as Helaric welding. Theevacuated envelope 12 is completed by a circular end plate 26 which issecured to a radially extending flange portion 27 associated with themounting cylinder 24. The mounting cylinder 24 and the plate 26 may bemade of a suitable conductive material such as Kovar. Within theevacuated envelope 12, there is disposed a cathode element 28 having anemissive coating thereon for the emission of an electron beam 39. Acontrol grid 30 is aligned with and disposed about the cathode element28 to modulate the density of the electron beam 39. An acceleratingelectrode 32 and pairs of horizontal deflection plates 36 and verticaldeflection plates 38 are aligned along the axis of the neck portion 14in the order enumerated to thereby accelerate and to deflect theelectron beam 39 in a regular pattern across a storage target 40 whichis disposed within the opposite end of the evacuated envelope 12.Further, a collecting electrode 47 which may be formed of a wire mesh isdisposed in a plane parallel and adjacent to the storage target 40.

The storage target 40 is mounted within the cylinder 24 by an annularmounting flange 42 which may be secured as by welding to the innerperiphery of the cylinder 24. A pluraliiy of support brackets 44 areinterconnected between the mounting flange 42 and the storage target 40.In one embodiment, the support brackets 44 are made of two Z-shapedstuds 45 which are respectively connected to the mounting flange 42 andthe storage target 48, and arc interconnected by an insulating bead 46of a suitable material such as glass which has been fused to the ends ofthe studs 45. A plurality of conductive leads 52 are electricallyconnected to the storage target 48. Further, a plurality of terminalelements 48 are disposed in a circular array through openings in themounting cylinder 24 to provide a vacuum sealed exit for each of theconductive leads 52. The terminal elements 48 are comprised of anannular eyelet 49 made of a suitable material .such as Kovar which maybe secured to the mounting cylinder 24 as by brazing with an alloy Ofcopper and silver. The conductive lead 52 which may likewise be made ofa material such as Kovar as insulated by a sleeve 50 made of a suitableinsulating material such as aluminum oxide which is disposed between theconductive lead 52 and the eyelet 49 to provide a vacuum sealtherebetween.

Referring now to FIG. 2, there is shown an enlarged view of the storagetarget 40 which is comprised of a crystal substrate 56 made of asemiconductor material such as silicon. A plurality of memory units 60have been diffused, as will be explained later, in a regular array 58comprised of horizontal rows 62 and vertical rows 64 of the memory units60. In the projected view of FIG. 2, a representation of the memory unit60 is shown; it may be understood, as will be explained later, that aninsulating layer 74 is disposed over each of the memory units 60. In oneembodiment as shown in FIG. 2, the memory unit 60 has a central region66 of a P-type semiconductive material which is successively surroundedby a region 68 of an N-type semiconductive material and a region of aP-type semiconductive material. Each of the memory units 60 iselectrically isolated from each other by a region 72 made of an N-typesemiconductor material.

Referring now to FIG. 3, a cross-sectioned view taken through lineIIIIII of FIG. 2, is shown. As shown in FIG. 3, the memory unit 60 hasthe stroage insulating layer 74 of a material such as silicon dioxidedisposed on one side and a second insulating layer 76 made of a similarmaterial disposed on the other side. As explained before, the centralregion 66 is surrounded successively by the region 68 and the region 70.A pair of low resistance contacts and 82 are inserted through theinsulating layer 76 to make an electrical connection respectively withthe region 70 and the region 66. In an alternate embodiment of thisinvention, contact 80 may be so placed to make electrical contact toboth of the regions 68 and 70. Rectifying junctions 67 and 69 are formedrespectively between regions 70 and 68 and between regions 68 and 66. Asexplained before, an isolating region 72 is disposed between each of thememory units 60; in the particular embodiment shown in FIG. 3, theregion 72 is made of an N-type semiconductive material and formsrectifying junctions 71 with the P-type region 70 of the adjacent memoryunits 60. A low resistance contact 81 may be inserted through theinsulating layer 76 upon which a positive voltage source 83 may beapplied to the N-type isolating region 72 to there by reverse bias therectifying junction 71 and effect a great isolation between the adjacentmemory units 60,

As will be explained later in detail, an inversion layer 73 is formedwithin the N-type region 68 due to the influence of charges deposited onthe storage insulating layer 74 by the electron beam 39. Though it isdesired to form such inversion layers in the region 68, this phenomenais undesired between the other regions; therefore, a plurality ofdiffusion regions 78 is formed by diffusing a high concentration ofN-type doping material within the regions of the N-type isolating region72 adjacent the insulating layers 74 and76. Further, a diffusion region78 is also formed within a layer of the N- type region 68 adjacent theinsulating layer 76. In order to make electrical connections with thecontact regions 80 and 82, a conductive leg 84 is vapor deposited overthe contact regions 80, and a vertical connecting strip 86 is vapordeposited over the contact regions 82.

Referring now to FIG. 4, a schematic representation of the equivalentelectrical circuit presented between the contact regions 80 and 82 isshown. Starting with contact- 80, the circuit can be traced through theP-type-region 70 across the rectifying junction 67, which is shown inFIG. 4 as a diode 67A. Next, a rectifying junction69 is formed at theboundary between the N-type region 68 and the P-type region 66 and isrepresented in FIG. 4.38 a diode 69A. Further,-the storage insulatinglayer 74 is represented with a plurality of negative charges placedthereon. The collecting electrode 47, which has been incorporated withinthe tube to limit the secondary current emitted by the target 40, isrepresented as being disposed in a plane parallel to the surface of theinsulating layer 74. I

In operation, the beam of electrons 39 is emitted by the cathode element28 and is successively modulated and accelerated by the electrodes 30and 32 respectively; further, the electron beam 39 is deflectedvertically and horizontally so as to pass over each of the memory units60 which are arrayed in the rows and columns shown in FIG. 2. As theelectron beam 39 passes over each of the memory units 60, it deposits aplurality of charges on the surface of the insulating layer 74.Referring now to FIG. 3, the inversion layer 73 is formed within theregion 68 due to the presence of the charges stored on the surface ofthe insulating layer 74. In effect, these chargesucreate a field whichrepels the negative charge carriers (i.e. electrons) and attracts thepositive charge carriers (i.e., holes). Thus, it may be understood thatthe impedance of the junctions 67 and 69 will .vary under the influenceof the negative charges. It hasbeen verified by experimentation that theconstant current characteristics of a rectifying junction such .as thejunctions 67 or 69 is proportional to the strength of an electricalfield such as created by the charges placed on the surface of theinsulatingilayer 74. With regard to. the specific embodiment shown inFIG. 3, the deposition of a negative charge on the insulating layer 74will repel the negative carriers within the N-type region 68 therebyeffecting a change of the impedance presented between the contactregions 80 and 82. It is an important aspect of this invention that thevoltage-current characteristic of rectifying junctions 69 may be variedat different levels according to the polarity and quantity of the chargedeposited' on the surfaceof the insulating layer 74. When a rectifyingjunction is impressed with a voltage in the reverse direction, theresulting saturation current is essentially independent of the magnitudeof the voltagefHowever, the saturation current may be changed byapplying an electrical field upon the junction. As explained above, thefield is established by depositing a charge upon the insulation layer 74which in turn controls the magnitude of saturation current passingthrough the junction 69 in accordance with the polarity and quantity ofdeposited charges. Thus, if a negative charge is placed upon theinsulation layer 74, the saturation current of the reverse biasedjunction 69 is increased, and conversely if a positive charge is placedupon layer 74, the saturation current is reduced. In the preferred modeof operation of this device, the electron beam 39 is accelerated by apotential less than that of the first crossover of the insulatingmaterial 74; thus negative charges are placed on the surface of theinsulating layer 74 to thereby lower the resistance presented by therectifying junction 69 when a reverse-bias voltage is subsequentlyapplied thereacross. As may be seen in FIG. 4, a positive voltage may beapplied to the contact region thereby forward biasing diode 67A andreverse biasing the diode 69A. The charges deposited upon the insulatinglayer 74 will control, as explained above, the saturation currentpassing through the diode 69A.

Further, it may be understood that if the electron beam 39 is directedupon the target 40 so that the dwell time upon each memory unit 60 willbe approximately equal, the density of the electron beam 39, which iscontrolled by the voltage applied to the control grid 30, will determinethe amount of charge placed upon the surface of the insulating layer 74.The amount of charge in turn will determine the voltage-currentcharacteristic of the rectifying junctions 67 and 69. The charges,stored on the surface of the dielectric layer or the insulating layer 74will remain substantially unaffected for extended periods of time andthereby provide a storage capability. When it is desifed to retrieve theinformation contained in the pattern of charges stored on the insulatinglayer 74 of the target 40, a voltage may be applied between the contacts80 and 82 to thereby reverse bias one of the rectifying junctions 67 and69. In a manner to be explained later, the reverse biasing voltage maybe successively applied across the memory units 60 to derive an outputsignal proportional to the voltage applied to the control grid 30. Ithas been found from actual experimentation, that a device substantiallyas shown in FIG. 3, was capable of storing a charge for a period of timein excess of hours. This prolonged storage capability was in part due tothe fact that the contacts 80 and 82 are isolated from the insulatinglayer 74 and thereby have little or no tendency to provide a groundingpath for the storage layer 74.

In a typical mode of operation, it would be desired, if not required,that the charge deposited on the insulating surface 74 be quickly andeasily removed so that a second pattern of charges could be depositedthereon. In a first mode of operation, the electron beam 39 could beaccelerated by a suitable potential to cause the breakdown of theinsulating layer 74 and :allow the charges to be dissipated through thesemiconductive regions to the various contacts associated therewith. Thepotential necessary to cause a breakdown of the insulating layer 74 isdependent upon the thickness of this layer; for a layer of an insulatinglayer 74 of silicon dioxide having a Width of approximately 1000Angstroms, a voltage level of between 60 to 100 volts has been foundsufficient for this mode of operation. In a second mode of operation,the electron beam is accelerated by a potential above the first cut-offof the material of the insulating layer 74; as a result, more secondaryemission electrons will be emitted than the number of electronsbombarding the insulating layer 74. Thus, an excess of electrons will bedissipated and collected by the electrode 47 which is disposed above theinsulating layer 74, thereby dissipating the charges from this layer.Though it has been assumed in this discussion that the priming orerasing electrons are supplied by the cathode elements 28 which wouldnecessitate blanking voltages being applied to the deflectionelectrodes, a separate electron gun could be provided within theenvelope 12 to accomplish the erasing of the target 40.

In an alternative embodiment of this invention, a metal layer 89 (shownin dotted line in FIG. 3) capable of emitting secondary electrons inresponse to an electron bombardment is disposed upon the insulationlayer 74 in proximity to that region 68 in which the inversion layer isto be formed. In such an embodiment, the region 68 would be diffusedwith P-type doping materials and the regions 70 and 66 would be diffusedwith N-type doping materials. Under the bombardment of electrons, thelayer 89 would emit secondary electrons which are collected by theelectrode 47. The surface of the layer 89 is thus driven positively to amagnitude controlled by the positive voltage applied to the electrode47. Thus, with a 7 positive charge disposed upon the layer 89, an N-typeinversion layer would be established within the region 68 and thecurrent characteristic of the junction 69 would be accordingly efiectedas explained above.

Though not a primary aspect of this invention, a typical procedure forforming the target of this invention will be briefly set out. First, asilicon ingot of the appropriate starting resistivity is cut, lapped toremove saw damage, polished to remove lapping damage and to approach thedesired final thickness, and then chemically etched or polished toprovide the appropriate wafer thickness and an essentially smoothsurface. The wafer of silicon is then subjected to a high temperatureusually greater than 100 C., in an oxidizing atmosphere which mayconsist of a wet non-oxidizing gas (such as nitrogen bubbled throughwater) and a dry oxygen or steam. The wafer is then coated with any ofthe well known acid resistance emulsions; next, a previously preparedphotographic negative is positioned over the wafer to obtain a maximumnumber of memory units 60 on the wafer and the emulsion is exposed to alight source. The wafer is then developed and the undesired silicondioxide may be removed in a hydrofluoric acid solution to provide anoxide pattern conforming to the negative. The remaining photoresist isthoroughly removed from the wafer by any of the well known solvents. Thewafer is now placed in a quartz boat and subjected to a first diffusionstep wherein appropriate doping materials are injected into thoseregions of the wafer in which the silicon dioxide has been removed.Typically, the doping materials for the P-type regions could be boronand the doping material for the N-type regions could be phosphorous. Incoincidence with the diffusion, or in the alternative as a separate stepfollowing the dilfusion, the oxide is regrown over the entire wafer. Thesteps of emulsion coating, alignment, developing, and oxide removal arerepeated before the wafer is subjected to a second diffusion to therebyimpart doping materials into different regions of the wafer. The wafermay proceed through several steps of diffusion in the same mannerdepending upon the complexity of the functional electronic block.Following the final diffusion, the areas of the wafer upon whichcontacts are to be placed may be metallized. Such materials as gold andaluminium are commonly used for metallization. In a typical method ofapplication, aluminium may be evaporated over the entire silicon wafer.The excess aluminium is removed by photoengraving techniques asdescribed above leaving aluminium contacts adhering to the silicon waferand aluminium interconnections to the silicon oxide layer. Following themetallization step to form contacts, a second metallization step isprovided to obtain interconnections with the conductive leads 52.Finally, the individual targets may be tested on a micromanipulator and,if satisfactory, may be inserted into the memory tube 10.

Referring now to FIG. 5, a view is shown of the reverse side of thetarget 40 upon which have been deposited electrical interconnections foreach of the memory units 60. As may be seen in FIG. 5, a plurality ofthe vertical connecting strips 86 may be vaporized on the insulatinglayer 76 so as to cover and contact each of the contacts 82. Further, itis noted that each of the vertical connecting strips 86 are disposedparallel with each other. A plurality of horizontal connecting strips 88are disposed in parallel rows with a plurality of conductive legs 84aligned perpendicular to the horizontal strips 88 to overlie and connectwith the contacts 80. Further, the conductive leads 52 may be connectedto the connecting strips 86 and 88 as by thermocompression bonding orultrasonic welding.

Referring now to FIG. 6, a cross-sectional view is shown of a portion ofthe target 40 depicting a structure by which the criss-crossing verticaland horizontal connecting strips 86 and 88 may be effectively insulatedfrom each other. As is shown in FIG. 6, the horizontal connecting strip88 is disposed above the isolating, N-type region 72; further, diffusionregions 78 are disposed upon either side of the region 72, and theinsulating storage layer 74 is disposed on one side of the region 72 andthe insulating layer 76 is disposed on the other side. The insulatedoverlapping of the connecting strips is achieved by disposing contactsthrough the insulating layer 76 and by interconnecting these contacts 95by a region 92 having a surplus of P-type doping material diffusedtherein. Further, a third insulating layer 94 is disposed above theregion 92, and thevertical connecting strip 86 may be deposited thereonto thereby achieve an effective insulation from the connecting strip 88.

Referring now to FIG. 7, a schematic representation of theinterconnections of the memory units 60 is shown. It is noted that onlya partial representation of the many memory units 60 is made, and thatin an actual embodiment of this invention as many as ten thousand memoryunits could be mounted on a target element having a diameter ofapproximately one inch. As shown in FIG. 7, a positive voltage sourcemay be successively applied by switches 96a, 96b, 960, etc., to thevertical connecting strips 86. The diodes 69a are interconnected betweenthe vertical connecting strips 86 and the horizontal connecting strips88 which may in turn be successively connected across a sensingimpedance 102 to ground by switches 98a, 98b, 980, etc. The signaloutput 104 is taken from the voltages developed across the sensingimpedance 102. Though only a single diode 69a has been represented inFIG. 7 whereas two diodes are represented in FIG. 4, it may beunderstood that if a positive voltage was applied to the contact 80 thatthe diode 67A (see FIG. 4) would be forward biased and would thereforeoffer little or no resistance in this circuit. In operation, it may beseen that if the switches 98a and 96a are both closed at once, that thevoltage source 100 will be impressed upon the diode 69a and a responsetherefrom will be detected upon the impedance 102. Thus, it may be seenthat each of the memory units 60 (as represented by a diode 69A) can besuccessively read out by closing switch 98a and then by successivelyopening and closing the switches desig nated by the numeral 6. The nextstep would be to open the switch 98a and then close the switch 98b andthen successively open and close those switches designated 96. In thismanner, the pattern of charges associated with each of the memory units60 may be successively read out one at a time.

Further, it is noted that the switching arrangement shown in FIG. 7 isonly an illustrative embodiment of how the memory units may be read out.A more complicated system of interconnections to the memory units couldbe devised so that more than one memory unit can be detected at the sametime. As previously discussed, each of the memory units are electricallyisolated from each other thereby allowing sections of the array ofmemory units to be operated in different modes of operation. Forinstance, the entire surface of the target 40 would not have to beprimed at a single time thereby allowing anew pattern of information tobe read on selected portions of the target while maintaining anotherpattern of information upon other sections of the target 40. Thisselection could be achieved by using grid blanking voltages, primaryvoltages, and input voltages that are synchronized in time with the beamdeflection signals.

Therefore, it may be realized that there has been disclosed a storagedevice in which there has been incorporated -a greatly improved storagetarget having a storage surface which has been effectively isolated fromthe external or adjacent circuitry to thereby achieve greatly increasedstorage times. Further, this target provides extremely fine resolution;in one embodiment of this invention, it has been found practical to forma target of 10,000 units having a spacing of from center to center ofapproximately five mils. Further, if the effective isolation betweenadjacent memory units is deleted, even greater numbers of memory unitsmay be placed upon the target.

An additional aspect of this invention is that very little power isrequired for the operation of this device; i.e., a signal is requiredfor the electron gun only during the write-in cycle, while no power isrequired for the electron gun and associated deflection plates duringthe storage time or read out.

. While there have been shown and described what are presentlyconsidered to be the preferred embodiments of the invention,modifications thereto will readily occur to those skilled in the art. Itis not desired, therefore, that the invention be limited to the specificarrangement shown and described and it is intended to cover in theappended claims all such modifications as fall within the true spiritand scope of the invention.

We claim as our invention:

1. An apparatus for the storage of electrical signals comprising a bodyof semiconductor material having first and second surfaces, a rectifyingjunction formed by regions of said body having differing conductivitytypes, a layer of storage material disposed on said first surface, andelectrical contacts in ohmic contact with said regions to provide acurrent flow to said junction, said contacts disposed on said secondsurface in a position electrically remote from said layer, and means fordirecting a flow of electrons onto said layer to produce a localizedcharge on said layer.

2. A storage target comprising a body of a semiconductor material havinga first and second surface, a plurality of memory units formed Withinsaid body in a regular array, said memory unit including a firstrectifying junction formed by regions of said body having differingtypes of conductivity types, a layer being disposed on said firstsurface and having the property of being able to store localizedcharges, electrical contacts in ohmic contact with said regions toprovide a current flow to said junction, said contacts being disposed onsaid second surface in a position remote from said layer, and means forisolating said memory units from each other including a secondrectifying junction formed by regions of said body having differingtypes of conductivity types.

3. A device for storing electrical signals comprising .a body ofsemiconductor material having first and second surfaces, a plurality ofmemory units formed within said 'body in a regular array of vertical andhorizontal rows, said memory unit including a first rectifying .junctionformed by first and second regions of differing conductivity types, afirst layer of storage material disposed on said first surface, a secondlayer of insulating material disposed on said second surface, at leastone contact associated with each of said first and second regions andextending through said second layer, means for isolating said memoryunits from each other including a second rectifying junction formed by athird and fourth region of said body having differing conductivitytypes, means for directing a fiow of electrons onto said layer toproduce a pattern of localized charges on said first layer, and meansfor detecting said pattern of charges including a plurality ofinterconnecting strips disposed on said second layer and electricallyconnected to said contacts.

4. A storage target comprising a body of semiconductor material havingfirst and second surfaces, a plurality of memory units formed Withinsaid body in a regular array, said memory unit including regions of saidbody of differing conductivity types to form a first P-N junctiontherebetween, electrical contact in ohmic contact with said regions toprovide a current flow to said first junction, and means forelectrically isolating said memory units from each other including asecond P-N junction formed by regions of said body having differingconductivity types.

5. A storage target comprising a body of semiconductor material havingfirst and second surfaces, a plurality of memory units formed withinsaid body in a regular array, said memory unit including first region, asecond region disposed about said first region, and a third regiondisposed about said second region, said second region having aconductivity type different from that of said first and third regions, alayer of storage material disposed on said first surface, contactsapplied to said first and third regions in a position on said secondsurface remote from said layer, and means for isolating said memoryunits from each other including a P-N junction formed by a fourth regionof said body and said third region, said fourth region having aconductivity type different from said third region.

6. A storage target comprising a body of semiconductor material havingfirst and second surfaces; a plurality of memory units formed withinsaid body in a regular array; said memory unit including a first region,a second region disposed about said first region, and a third regiondisposed about said second region, said first and third regions having aconductivity type different from that of said second region to formfirst and second rectifying junctions between said first and secondregions, and between said second and third regions respectively; a layerof storage material applied to said first surface, at least one contactapplied on said second surface to each of said first and third regions;and means for isolating said memory units from each other including afourth region disposed about said third region, said fourth regionhaving a conductivity type different from that of said third region toform third rectifying junctions therebetween.

7. A storage target comprising a body of semiconductor material having afirst and second surface; a plurality of memory units formed from saidbody in a regular array; each of said memory units including a first P-Njunction formed by first and second regions of said body havingdiffering types of semiconductivity, a layer formed on said firstsurface having the capability of storing a pattern of localized charges,said charges forming an inversion layer in said second region adjacentsaid layer to thereby effect the impedance of said first P-N junction,electrical contacts disposed on said second surface in electricalassociation with said first and second regions to provide a current flowto said first P-N junction, and means for isolating said memory unitsfrom each other including a third region of said body disposed aboutsaid memory unit and a zone in said third region having a surplusquantity of a doping material diffused therein to prevent the formationof an inversion layer.

8. A storage target comprising a body of semiconductor material havingfirst and second surfaces; a plurality of memory unit-s formed withinsaid body in a regular array; said memory unit including a firstrectifying junction' formed by first and second regions of said bodyhaving differing conductivity types, and a layer disposed on said firstsurface capable of storing a pattern of localized chrages, said chargesforming an inversion layer in said second region to effect thevoltage-current characteristics of said first junction; electricalcontacts disposed on said second surface in electrical association withsaid first and second regions to provide a current flow to said firstjunction; and means for isolating said memory units from each otherincluding a second rectifying junction formed by third and fourthregions of said body having differing conductivity types and a zoneWithin said fourth region having an added quantity of doping materialdiffused therein to prevent the formation of an inversion layer.

9. A storage target comprising a body of semiconductor material havingfirst and second surfaces; a plurality of memory units formed withinsaid body in a regular array; said memory units including a firstregion, a second region disposed about said first region, and a thirdregion disposed about said second region, said first and third regionshaving a conductivity type differing from that of said second region toform first and second P-N junctions respectively between said first andsecond regions and between said second and third regions, and a layerdisposed on said first surface capable of storing a pattern of localizedcharges, said charges forming an inversion layer in said second regionthereby effecting the impedance presented by said first and secondjunctions; electrical contacts disposed on said second surface in ohmiccontact with said first and third regions; and means for isolating saidmemory units from each other including a fourth region disposed aboutsaid memory units and having a conductivity type differing from that ofsaid third region to form a third P-N junction therebetween, and a zoneformed Within said fourth region adjacent said layer having an addedquantity of doping material diffused therein to prevent the formation ofan inversion layer.

10. A storage device comprising a body of semiconductor material havingfirst and second surfaces; a plurality of memory units formed withinsaid body in a regular array; said memory units including a firstrectifying junction formed by first and second regions of differentconductivity types, and a layer of storage material disposed on saidfirst surface; contacts disposed on said second surface in a positionremote from said layer in electrical association with said first andsecond regions to provide a current fiow to said first junction; andmeans for electrically isolating said memory units from each otherincluding a second rectifying junction formed by third and fourthregions of said body of different conductivity types; and means forapplying a potential to said fourth region to increase the impedance ofsaid second junction.

11. A storage target comprising a body of semiconductor material havingfirst and second surfaces; a plurality of memory units formed withinsaid body in a regular array; said memory units including a rectifyingjunction formed by a first region of P-type conductivity and a secondregion of N-type conductivity within said body, a first layer of storagematerial disposed on said second surface, and a second layer beingdisposed on said first layer in proximity to said first region andhaving the property of emitting sceondary electrons in response to aflow of primary electrons; and contacts disposed on said second surfacein electrical association with said first and second regions to providea current fiow to said junction.

12. A device for storing electrical signals comprising a target element,said target element including a body of semiconductor material havingfirst and second surfaces, a plurality of memory units formed withinsaid body and having a P-N junction formed by regions of said bodyhaving differing conductivity types, a storage layer formed on saidfirst surface, and contacts disposed on said second surface in ohmiccontact with said regions to provide a current fiow to said junction;means for placing said electrical signals on said target including acathode element for directing a fiow of electrons on said targetelement; and means for retrieving said electrical signals including aplurality of electrical connections to said contacts, and means forselectively applying a reverse biasing potential in a determined orderto said connections.

13. A device for storing electrical signals comprising a target element,said target element including a body of semiconductor material havingfirst and second surfaces, a plurality of memory units formed Withinsaid body and including a first region, a second region disposed aboutsaid first region, and a third region of said body disposed about saidsecond region, said first and third regions having conductivity typesdiffering from that of said second region to form first and second P-Njunctions respectively between said first and second regions and betweensaid second and third regions, a storage layer disposed upon said firstsurface, contacts disposed upon said first and third regions on saidsecond surface, and means for isolating said memory units from eachother including a fourth region of said body having a conductivity typediffering from that of said third region to form a third P-N junctionbetween said third and fourth regions; means for writing including acathode gun for directing a beam of electrons across said target elementto thereby dispose a pattern of localized charges upon said layer; andmeans for reading including a plurality of electrical conductorsconnected to said contacts, and switching means for selectively applyinga reverse biasing potential to said conductors to sense said pattern oflocalized charges. 9

14. A device for storing electrical signals comprising a target element,said target element including a .bodyof semiconductor material havingfirst and second surfaces, a plurality of memory units formed withinsaid body and including a first rectifying junction formed by first andsecond regions of said body having differing conductivity types, astorage layer disposed on said first surface, first contactselectrically associated with each of'said first and second regions anddisposed on said second surface; and means for isolating each of saidmemory units from each other including a second rectifying junctionformed by third and fourth regions of said body having differingconductivity types, second contacts associated with said fourth region,and means for applying a potential to said second contacts to increasethe impedance presented by said second junction, means for writingincluding a cathode gun for directing a beam of electrons on said targetelement to thereby impart a pattern of localized charges upon thesurface of said layer; and means for reading including switching meansfor selectively applying a reverse biasing potential to said firstcontacts to thereby sense said pattern of localized charges.

15. A storage target comprising a body of semiconductor material inwhich a plurality of memory units are formed, each of said memory unitsincluding first, second and third regions, said second region disposedbetween said first and second regions and having a conductivity typedifferent from that of said first and second regions to formrespectively first and second junctions between said first and secondregions and between said second and third regions, said second regioncapable of forming an inversion layer therein, a layer of storagematerial disposed upon said storage target and capable of storing anelectrical charge thereon to induce the formation of said inversionlayer in said second region, and means for isolating said memory unitsfrom each other including a fourth region disposed about each of saidmemory units.

16. A storage target comprising a body of semiconductor material havingfirst and second surfaces; a plurality of memory units formed Withinsaid body in a regular array, each of said memory units including afirst region, a second region disposed about said first region, and athird region disposed about said second region, said second regionhaving a conductivity type different from that of said first and secondregions to form first and second rectifying junctions between said firstand second regions and between said second and third regionsrespectively, said second region capable of forming an inversion regiontherein, and a layer of storage material applied to said first surfacecapable of storing electrical charges to effect said inversion regionwithin said second region.

17. A storage target as claimed in claim 16, wherein contacts areapplied to said first and third regions on said second surface to effecta current flow to said first and second rectifying junctions.

References Cited UNITED STATES PATENTS 2,547,386 4/1951 Gray 3281232,592,683 4/1952 Gray 3l535 X 2,860,282 11/1958 Hansen 315- 3,020,4382/1962 Sziklai 315-1 ROBERT SEGAL, Primary Examiner.

JAMES W. LAWRENCE, Examiner.

11. A STORAGE TARGET COMPRISING A BODY OF SEMICONDUCTOR MATERIAL HAVINGFIRST AND SECOND SURFACES; A PLURALITY OF MEMORY UNITS FORMED WITHINSAID BODY IN A REGULAR ARRAY; SAID MEMORY UNITS INCLUDING A RECTIFYINGJUNCTION FORMED BY A FIRST REGION OF P-TYPE CONDUCTIVITY AND A SECONDREGION OF N-TYPE CONDUCTIVITY WITHIN SAID BODY, A FIRST LAYER OF STORAGEMATERIAL DISPOSED ON SAID SECOND SURFACE, AND A SECOND LAYER BEINGDISPOSED ON SAID FIRST LAYER IN PROXIMITY TO SAID FIRST REGION ANDHAVING THE PROPERTY OF EMITTING SECONDARY ELECTRONS IN RESPONSE TO